1. Field of the Invention
The present invention relates to an output circuit for converting an internal power supply potential into an external power supply potential in a semiconductor apparatus such as a semiconductor storage device using the internal power supply potential at which the external power supply potential is voltage reduced. In particular, the present invention relates to an output circuit for the purpose of speedy voltage conversion and prevention of a penetration current.
2. Description of the Related Art
In recent years, in a semiconductor storage device, with advancement of fineness, the withstand voltage of a cell transistor configuring the semiconductor storage device is reduced. Because of this, there has been developed a semiconductor storage device that incorporates a voltage reducing circuit in a chip to reduce an external power supply voltage to an allowable transistor withstand voltage, and that uses this voltage as an internal power supply potential for driving the cell transistor. In this case, with respect to an output of the semiconductor storage device, it is require to convert the voltage from an internal power supply voltage to an external power supply voltage in an output circuit in order to output specification. The output circuit itself uses an external power supply potential at which a voltage is not reduced.
Recently, a difference between the internal power supply potential and the external power supply potential increases, and a delay in voltage level conversion becomes an obstacle in speedy conversion. In addition, a penetration current flows at a level converting portion, causing an increase in current consumption.
Conventionally, in an EL (electro luminescence) display panel driving circuit, in order to reduce power consumption, there has been disclosed an output stage circuit in which an auxiliary level shift circuitry is disposed at a previous stage of a level shift circuitry for driving an output transistor that consists of a p-channel transistor and an n-channel transistor, thereby, even if a grounding potential at a high voltage power supply side fluctuates, making it possible to avoid an incorrect drive of the level shift circuitry at the high voltage power supply side and to avoid an unwanted penetration current in an output transistor (Japanese Patent Application Laid-open No. 6-46360).
However, the output stage circuit described in this publication is such that a reference potential line is separated into an input side grounding wire GND 1 and an output side grounding wire GND 2 in order to prevent an unclear grounding potential that corresponds to a low level of an input signal IN as a result of a level shift output voltage of an EL display panel driving circuit being returned to an input side. In this case, unlike a case of a semiconductor storage device such as DRAM, a technique described in the publication could not be applied intact to prevent a penetration current of a semiconductor storage device, and a read/write speed could not be reduced in the prior art.
It is an object of the present invention to provide an output circuit capable of reading and writing at a high speed data on semiconductor storage device with the advancement of fineness and the achievement of a low voltage of an internal power supply potential, the output circuit being capable of preventing a penetration current and significantly reducing current consumption.
According to one aspect of the present invention, there is provided an output circuit comprising:
a three-state buffer circuit having a pull-up side transistor and a pull-down side transistor connected in series between an external power supply potential and a grounding voltage;
an output terminal connected to a node between the pull-up side transistor and the pull-down side transistor buffer circuit;,
a first level shift circuitry connected to a gate of the pull-up side transistor, the first level shift circuitry converting a voltage of an input signal from an internal power supply potential lower than the external power supply potential to the external power supply potential;
a second level shift circuitry connected to a gate of the pull-down side transistor, the second level shift circuitry converting a voltage of an input signal from the internal power supply potential to the external power supply potential;
a signal change detecting circuit for detecting a change of the input signal; and
a delay circuitry for delaying an output signal of this signal change detecting circuit to output to the first and second level shift circuitry a signal; for controlling an output of an output circuit to be active or inactive, wherein, when the control signal is in a first state, either one of the pull-up side transistor and pull-down side transistor is turned OFF, causing the output terminal to enter a high impedance, and when the control signal is in a second state, a signal according to xe2x80x9chighxe2x80x9d or xe2x80x9clowxe2x80x9d of the input signal is outputted to the output terminal.
According to another aspect of the present invention, there is provided an output circuit comprising:
a three-state buffer circuit having a pull-up side transistor and a pull-down side transistor connected in series between an external power supply potential and a grounding voltage;
an output terminal connected to a node between the pull-up side transistor and the pull-down side transistor;
a first level shift circuitry connected to a gate of the pull-up side transistor, the first level shift circuitry converting a voltage of a data signal from an internal power supply potential lower than the external power supply potential to the external supply potential;
a second level shift circuitry connected to a gate of side pull-down side transistor, the second level shift circuitry converting a voltage of the data signal from an internal power supply potential to the external power supply potential;
a signal change detecting circuit for detecting a change of the data signal;
a delay circuitry for delaying an output signal of this signal change detecting circuit to output to the first and second level shift circuitry a signal for controlling an output of an output circuit to be active or inactive;
a NAND circuit to which the data signal and the control signal are inputted;
an NOR circuit to which the data signal and an inverting signal of the control signal are inputted; and
an inverter connected between an output end of the second level shift circuitry and a gate of the pull-down side transistor, wherein, when the control signal is in a first state, either one of the pull-up side transistor and pull-down side transistor is turned OFF, causing the output terminal to enter a high impedance, and when the control signal is in a second state, a signal according to xe2x80x9chighxe2x80x9d or xe2x80x9clowxe2x80x9d of the input signal is outputted to the output terminal.
In this case, the output circuit can be configured so that the first level shift circuitry comprises:
a first node to which an inverting signal of an output signal of the NAND circuit;
a second node connected to a gate of the pull-down side transistor;
a second conductive MOS second transistor connected between the external power supply potential and the third node; and
a second conductive MOS third transistor and a first conductive MOS fourth transistor connected in series between the external power supply potential and a grounding potential, wherein the internal power supply potential is provided to a gate of the first transistor, the second node is connected to a gate of the second transistor, the third node is connected to a gate of the third transistor, the second node is connected to a connection point between the third transistor and the fourth transistor, and
the second level shift circuitry comprises:
a fourth node to which an output signal of the NOR circuit is inputted;
a fifth node connected to the inverter;
a sixth node;
a first conductive MOS fifth transistor connected between the fourth node and the sixth node;
a second conductive MOS sixth transistor connected between an external power supply potential and the sixth node;
a second conductive MOS seventh transistor and a first conductive MOS eighth transistor connected in series between the external power supply potential and a grounding potential, wherein an internal power supply potential is provided to a gate of the fifth transistor, the fifth node is connected to a gate of the sixth transistor, the sixth node is connected to a gate of the seventh transistor, the fourth node is connected to a gate of the eighth transistor, and the fifth node is connected to a connection point between the seventh transistor and the eighth transistor.
In addition, the output circuit can be configured so that the first level shift circuitry comprises:
a second conductive MOS first transistor and a first conductive MOS second transistor connected in series between the external power supply potential and a grounding potential;
a second conductive MOS third transistor and a first conductive MOS fourth transistor connected in series between the external power supply potential and the grounding potential;
a first node to which an output signal of the NAND circuit is inputted;
a second node connected to a gate of the pull-up side transistor, the second node being connected to a connection point between the third transistor and the fourth transistor:
a third node connected to a connection point between the first transistor and the second transistor; and
a second inverter connected between the first node and gate of the fourth gate transistor, wherein the first node is connected to a gate of the second transistor, and
the second level shift circuitry comprises:
a second conductive MOS fifth transistor and a first conductive MOS sixth transistor connected in series between the external power supply potential and the grounding potential;
a second conductive MOS seventh transistor and a first conductive MOS eighth transistor connected in series between the external power supply potential and the grounding potential;
a fourth node to which an output signal of the NOR circuit is inputted;
a fifth node connected to the inverter, the fifth node being connected to a connection point between the seventh transistor and the eighth transistor;
a sixth node connected to a connection point between the fifth transistor and the sixth transistor; and
a third inverter connected between the fourth node and a gate of the sixth transistor, wherein the fourth node is connected to a gate of the eighth transistor.
In the present invention, a level shift circuitry is incorporated in an output circuit in order to eliminate the penetration current during level conversion that is a disadvantage of the prior art. In general, the level shift circuitry is characterized in that a L (low) output is quick, and a H (high) output is slow. Thus, the level shift circuitry is disposed so that DOUT enters a high impedance when a level shift output is slow (H). Further, while in a read state, when read operation starts after an address has been changed, a DOUT circuit is temporarily set to be inactive before readout data is outputted from a memory cell. Then, the readout data is determined, and at the same time, DOUT is controlled so as to be active, thereby making it possible to prevent both of the output transistors from turning ON at the same time, and further, making it possible to cause operation at a high speed.